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2549ks?avr?01/07 features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 135 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier ? non-volatile progra m and data memories ? 64k/128k/256k bytes of in-system self-programmable flash endurance: 10,000 write/erase cycles ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-w rite operation ? 4k bytes eeprom endurance: 100,000 write/erase cycles ? 8k bytes internal sram ? up to 64k bytes optional external memory space ? programming lock for software security ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities a ccording to the jtag standard ? extensive on-chip debug support ? programming of flash, eeprom, fuses, an d lock bits through the jtag interface ? peripheral features ? two 8-bit timer/counters with se parate prescaler and compare mode ? four 16-bit timer/counter with separate prescaler, compare- and capture mode ? real time counter with separate oscillator ? four 8-bit pwm channels ? six/twelve pwm channels with programma ble resolution from 2 to 16 bits (atmega1281/2561, atmega640/1280/2560) ? output compare modulator ? 8/16-channel, 10-bit adc (atmega1281/2561, atmega640/1280/2560) ? two/four programmable serial usart (atmega1281/2561,atmega640/1280/2560) ? master/slave spi serial interface ? byte oriented 2-wire serial interface ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? six sleep modes: idle, adc noise reduction, power-save, power-down, standby, and extended standby ? i/o and packages ? 54/86 programmable i/o lines (atmega1281/2561, atmega640/1280/2560) ? 64-pad qfn/mlf, 64-lead tqfp (atmega1281/2561) ? 100-lead tqfp, 100-ball cbga (atmega640/1280/2560) ? rohs/fully green ? temperature range: ?-40 c to 85 c industrial ? ultra-low power consumption ? active mode: 1 mhz, 1.8v: 510 a ? power-down mode: 0.1 a at 1.8v ? speed grade (see ?maximum sp eed vs. vcc? on page 377): ? atmega640v/atmega1280v/atmega1281v: 0 - 4 mhz @ 1.8 - 5.5v, 0 - 8 mhz @ 2.7 - 5.5v ? atmega2560v/atmega2561v: 0 - 2 mhz @ 1.8 - 5.5v, 0 - 8 mhz @ 2.7 - 5.5v ? atmega640/atmega1280/atmega1281: 0 - 8 mhz @ 2.7 - 5.5v, 0 - 16 mhz @ 4.5 - 5.5v ? atmega2560/atmega2561: 0 - 16 mhz @ 4.5 - 5.5v 8-bit microcontroller with 64k/128k/256k bytes in-system programmable flash atmega640/v atmega1280/v atmega1281/v atmega2560/v atmega2561/v preliminary summary
2 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 pin configurations figure 1. tqfp-pinout atmega640/1280/2560 gnd v cc pa0 (ad0) pa1 (ad1) pa2 (ad2) pa3 (ad3) pa4 (ad4) pa5 (ad5) pa6 (ad6) pa7 (ad7) pg2 (ale) a v c c gnd aref pf0 (adc0) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) pf7 (adc7/tdi) atme g a640/12 8 0/2560 100 99 9 8 97 96 95 94 93 92 91 90 8 9 88 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0797 8 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 8 19 20 21 22 23 24 25 75 74 73 72 71 70 69 6 8 67 66 65 64 63 62 61 60 59 5 8 57 56 55 54 53 52 51 26 2 8 29 31 27 36 30 32 35 37 33 34 3 8 39 40 41 42 43 44 45 46 47 4 8 49 50 pk0 (adc 8 /pcint16) pk1 (adc9/pcint17) pk2 (adc10/pcint1 8 ) pk3 (adc11/pcint19) pk4 (adc12/pcint20) pk5 (adc13/pcint21) pk6 (adc14/pc int22) pk7 (adc15/pc int23) (oc2b) ph6 (tosc2) pg3 (tosc1) pg4 reset (t4) ph7 (icp4) pl0 v cc gnd xtal2 xtal1 pl6 pl7 gnd v cc (oc0b) pg5 v cc gnd (rxd2) ph0 (txd2) ph1 (xck2) ph2 (oc4a) ph3 (oc4b) ph4 (oc4c) ph5 (rxd0/pcint 8 ) pe0 (txd0) pe1 (xck0/ain0) pe2 (oc3a/ain1) pe3 (oc3b/int4) pe4 (oc3c/int5) pe5 (t3/int6) pe6 (clko/icp3/int7) pe7 (ss/pcint0) pb0 (sck/pcint1) pb1 (mosi/pcint2) pb2 (miso/pcint3) pb3 (oc2a/pcint4) pb4 (oc1a/pcint5) pb5 (oc1b/pcint6) pb6 (oc0a/oc1c/pcint7) pb7 pc7 (a15) pc6 (a14) pc5 (a13) pc4 (a12) pc3 (a11) pc2 (a10) pc1 (a9) pc0 (a 8 ) pg1 (rd) pg0 (wr) (txd1/int3) pd3 (icp1) pd4 (xck1) pd5 (t1) pd6 (t0) pd7 (scl/int0) pd0 (sda/int1) pd 1 (rxd1/int2) pd2 (icp5) pl1 (t5) pl2 (oc5a) pl3 (oc5b) pl4 pj6 (pcint15) pj5 (pcint14) pj4 (pcint13) pj3 (pcint12) pj2 (xck3/pcint11) pj1 (txd3/pcint10) pj0 (rxd3/pcint9) pj7 (oc5c) pl5 index corner
3 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 figure 2. cbga-pinout atmega640/1280/2560 table 1. cbga-pinout atmega640/1280/2560. 12 345678910 a g n d aref pf0 pf2 pf5 pk0 pk3 pk6 g n dvcc b avcc pg5 pf1 pf3 pf6 pk1 pk4 pk7 pa0 pa2 c pe2 pe0 pe1 pf4 pf7 pk2 pk5 pj7 pa1 pa3 d pe3 pe4 pe5 pe6 ph2 pa4 pa5 pa6 pa7 pg2 e pe7 ph0 ph1 ph3 ph5 pj6 pj5 pj4 pj3 pj2 f vcc ph4 ph6 pb0 pl4 pd1 pj1 pj0 pc7 g n d g g n d pb1 pb2 pb5 pl2 pd0 pd5 pc5 pc6 vcc h pb3 pb4 reset pl1 pl3 pl7 pd4 pc4 pc3 pc2 j ph7 pg3 pb6 pl0 xtal2 pl6 pd3 pc1 pc0 pg1 k pb7 pg4 vcc g n d xtal1 pl5 pd2 pd6 pd7 pg0 a b c d e f g h j k 1 2345678910 a b c d e f g h j k 1098765432 1 top view bottom view
4 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 figure 3. pinout atmega1281/2561 n ote: the large center pad underneath the qf n /mlf package is made of metal and internally connected to g n d. it should be soldered or glued to the board to ensure good mechani- cal stability. if the center pad is left uncon nected, the package might loosen from the board. disclaimer typical values contained in this datasheet are based on simulations and characteriza- tion of other avr microcontrollers manufactured on the same process technology. min. and max values will be available afte r the device is characterized. atmega12 8 1/2561 (rxd0/pcint8/pdi) pe0 (txd0/pdo) pe1 (xck0/ain0) pe2 (oc3a/ain1) pe3 (oc3b/int4) pe4 (oc3c/int5) pe5 (t3/int6) pe6 (icp3/clko/int7) pe7 (ss/pcint0) pb0 (oc0b) pg5 (sck/ pcint1) pb1 (mosi/ pcint2) pb2 (miso/ pcint3) pb3 (oc2a/ pcint4) pb4 (oc1a/pcint5) pb5 (oc1b/pcint6) pb6 (oc0a/oc1c/ pcint7 ) pb7 (tosc2) pg3 (tosc1) pg4 reset vcc gnd xtal2 xtal1 (scl/int0) pd0 (sda/int1 ) pd1 (rxd1/int2) pd2 (txd1/int3) pd3 (icp1) pd4 (xck1) pd5 pa3 (ad3) pa4 (ad4) pa5 (ad5) pa6 (ad6) pa7 (ad7) pg2 (ale) pc7 (a15) pc6 (a14) pc5 (a13) pc4 (a12) pc3 (a11) pc2 (a10) pc1 (a9) pc0 (a8) pg1 (rd) pg0 (wr) avcc gnd aref pf0 (adc0) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms ) pf6 (adc6/tdo) pf7 (adc7/tdi) gnd vcc pa0 (ad0) pa 1 (ad1) pa 2 (ad2) (t1) pd6 (t0) pd7 index corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
5 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 overview the atmega640/1280/1281/2560/2561 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the atmega640/1280/1281/2560/2561 achieves throughputs appr oaching 1 mips per mhz allowing th e system designer to optimize po wer consumption versus processing speed. block diagram figure 4. block diagram cpu g n d vcc reset power supervision por / bod & reset w atchdog oscillator w atchdog timer oscillator circuits / clock generation xtal1 xtal2 pc7..0 port c (8) pa7..0 port a (8) port d (8) pd7..0 port b (8) pb7..0 port e (8) pe7..0 port f (8) pf7..0 port j (8) pj7..0 pg5..0 port g (6) port h (8) ph7..0 port k (8) pk7..0 port l (8) pl7..0 xram t w i spi eeprom jtag 8bit t/c 0 8bit t/c 2 16bit t/c 1 16bit t/c 3 sram flash 16bit t/c 4 16bit t/c 5 usart 2 usart 1 usart 0 internal bandgap reference analog comparator a/d converter usart 3 note: shaded parts only available in the 100-pin version. complete functionality for the adc, t/c4, and t/c5 only available in the 100-pin version.
6 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 the avr core combines a rich instruction se t with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the atmega640/1280/1281/2560/2561 provides the following features: 64k/128k/256k bytes of in-system programmable flash with read- w hile- w rite capabilities, 4k bytes eeprom, 8k bytes sram, 54/86 general purpose i/o lines, 32 general purpose work- ing registers, real time counter (rtc), six flexible timer/counters with compare modes and p w m, 4 usarts, a byte oriented 2-wire serial interface, a 16-channel, 10- bit adc with optional differential input st age with programmable gain, programmable w atchdog timer with internal oscillator, an spi serial port, ieee std. 1149.1 compliant jtag test interface, also used for accessing the on-chip debug system and program- ming and six software selectable power saving modes. the idle mode stops the cpu while allowing the sram, time r/counters, spi port, and interrupt system to continue functioning. the power-down mode saves the register contents bu t freezes the oscilla- tor, disabling all other chip functions unt il the next interrupt or hardware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to main- tain a timer base while the rest of the device is sleeping. the adc n oise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc, to min- imize switching noise during adc conversions. in standby mode, the crystal/resonator oscillator is running while the re st of the device is sleeping. this allows very fast start-up combined with low power consumption. in extended standby mode, both the main oscillator and the a synchronous timer continue to run. the device is manufactured using atmel?s hi gh-density nonvolatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the application flash memory. soft- ware in the boot flas h section will continue to run while the application flash section is updated, providing true read- w hile- w rite operation. by combining an 8-bit risc cpu with in-system self-programmable fl ash on a monolithic chip, the atmel atmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the atmega640/1280/1281/2560/2561 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
7 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 comparison between atme ga1281/2561 and at mega640/1280/2560 each device in the atmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. table 2 summarizes the different configurations for the six devices. pin descriptions vcc digital supply voltage. gnd ground. port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the atmega640/1280/1281/2560/2561 as listed on page 91. port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b has better driving ca pabilities than th e other ports. port b also serves the functions of various special features of the atmega640/1280/1281/2560/2561 as listed on page 92. port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port c pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of special features of the atmega640/1280/1281/2560/2561 as listed on page 95. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port d pi ns that are externally pulled low will source table 2. configuration summary device flash eeprom ram general purpose i/o pins 16 bits resolution pwm channels serial usarts adc channels atmega640 64kb 4kb 8kb 86 12 4 16 atmega1280 128kb 4kb 8kb 86 12 4 16 atmega1281 128kb 4kb 8kb 54 6 2 8 atmega2560 256kb 4kb 8kb 86 12 4 16 atmega2561 256kb 4kb 8kb 54 6 2 8
8 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the atmega640/1280/1281/2560/2561 as listed on page 97. port e (pe7..pe0) port e is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the atmega640/1280/1281/2560/2561 as listed on page 99. port f (pf7..pf0) port f serves as analog inputs to the a/d converter. port f also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port f output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are activated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. if th e jtag interface is enabled, the pull-up resis- tors on pins pf7(tdi), pf 5(tms), and pf4(tck) will be activated even if a reset occurs. port f also serves the functions of the jtag interface. port g (pg5..pg0) port g is a 6-bit i/o port with internal pull-up resistors (selected for each bit). the port g output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port g pins that are ex ternally pulled low will source current if the pull-up resistors are activated. the port g pins are tri-stated when a reset condition becomes active, even if the clock is not running. port g also serves the functions of various special features of the atmega640/1280/1281/2560/2561 as listed on page 105. port h (ph7..ph0) port h is a 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port h output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port h pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port h pins are tri-stated when a reset condition becomes active, even if the clock is not running. port h also serves the functions of various special features of the atmega640/1280/2560 as listed on page 107. port j (pj7..pj0) port j is a 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port j output buffers have symmetric al drive characteristics with both high sink and source capability. as inpu ts, port j pins that are externally pulled low will source current if the pull-up resistors are activated. the port j pins are tri-stated when a reset condition becomes active, even if the clock is not running. port j also serves the functions of various special features of the atmega640/1280/2560 as listed on page 109. port k (pk7..pk0) port k serves as analog inputs to the a/d converter.
9 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 port k is a 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port k output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port k pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port k pins are tri-stated when a reset condition becomes active, even if the clock is not running. port k also serves the functions of various special features of the atmega640/1280/2560 as listed on page 111. port l (pl7..pl0) port l is a 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port l output buffers have symmetri cal drive characteristics with both high sink and source capability. as inputs, port l pins that are externally pulled low will source current if the pull-up resistors are activated. the port l pins are tri-stated when a reset condition becomes active, even if the clock is not running. port l also serves the functions of various special features of the atmega640/1280/2560 as listed on page 113. reset reset input. a low level on this pin for longer than the minimu m pulse length will gener- ate a reset, even if the clock is not running. the minimum pulse length is given in table 26 on page 58. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. xtal2 output from the invert ing oscillator amplifier. avcc avcc is the supply voltage pin for port f and the a/d converter. it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be con- nected to v cc through a low-pass filter. aref this is the analog reference pin for the a/d converter. resources a comprehensive set of development tools and application notes, and datasheets are available for download on http://www.atmel.com/avr.
10 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0x1ff) reserved - - - - - - - - ... reserved - - - - - - - - (0x13f) reserved (0x13e) reserved (0x13d) reserved (0x13c) reserved (0x13b) reserved (0x13a) reserved (0x139) reserved (0x138) reserved (0x137) reserved (0x136) udr3 usart3 i/o data register page 227 (0x135) ubrr3h - - - - usart3 baud rate register high byte page 231 (0x134) ubrr3l usart3 baud rate register low byte page 231 (0x133) reserved - - - - - - - - (0x132) ucsr3c umsel31 umsel30 upm 31 upm30 usbs3 ucsz31 ucsz30 ucpol3 page 244 (0x131) ucsr3b rxcie3 txcie3 udrie3 rxe n 3txe n 3 ucsz32 rxb83 txb83 page 243 (0x130) ucsr3a rxc3 txc3 udre3 fe3 dor3 upe3 u2x3 mpcm3 page 242 (0x12f) reserved - - - - - - - - (0x12e) reserved - - - - - - - - (0x12d) ocr5ch timer/counter5 - output compare register c high byte page 167 (0x12c) ocr5cl timer/counter5 - output compare register c low byte page 167 (0x12b) ocr5bh timer/counter5 - output compare register b high byte page 167 (0x12a) ocr5bl timer/counter5 - output compare register b low byte page 167 (0x129) ocr5ah timer/counter5 - output compare register a high byte page 167 (0x128) ocr5al timer/counter5 - output compare register a low byte page 167 (0x127) icr5h timer/counter5 - input capture register high byte page 168 (0x126) icr5l timer/counter5 - input capture register low byte page 168 (0x125) tc n t5h timer/counter5 - counter register high byte page 165 (0x124) tc n t5l timer/counter5 - counter register low byte page 165 (0x123) reserved - - - - - - - - (0x122) tccr5c foc5a foc5b foc5c - - - - - page 164 (0x121) tccr5b ic n c5 ices5 - w gm53 w gm52 cs52 cs51 cs50 page 162 (0x120) tccr5a com5a1 com5a0 com5b1 com5b0 com5c1 com5c0 w gm51 w gm50 page 160 (0x11f) reserved - - - - - - - - (0x11e) reserved - - - - - - - - (0x11d) reserved - - - - - - - - (0x11c) reserved - - - - - - - - (0x11b) reserved - - - - - - - - (0x11a) reserved - - - - - - - - (0x119) reserved - - - - - - - - (0x118) reserved - - - - - - - - (0x117) reserved - - - - - - - - (0x116) reserved - - - - - - - - (0x115) reserved - - - - - - - - (0x114) reserved - - - - - - - - (0x113) reserved - - - - - - - - (0x112) reserved - - - - - - - - (0x111) reserved - - - - - - - - (0x110) reserved - - - - - - - - (0x10f) reserved - - - - - - - - (0x10e) reserved - - - - - - - - (0x10d) reserved - - - - - - - - (0x10c) reserved - - - - - - - - (0x10b) portl portl7 portl6 portl5 portl4 portl3 portl2 portl1 portl0 page 118 (0x10a) ddrl ddl7 ddl6 ddl5 ddl4 ddl3 ddl2 ddl1 ddl0 page 118 (0x109) pi n lpi n l7 pi n l6 pi n l5 pi n l4 pi n l3 pi n l2 pi n l1 pi n l0 page 118 (0x108) portk portk7 portk6 portk5 portk4 portk3 portk2 portk1 portk0 page 118 (0x107) ddrk ddk7 ddk6 ddk5 ddk 4 ddk3 ddk2 ddk1 ddk0 page 118 (0x106) pi n kpi n k7 pi n k6 pi n k5 pi n k4 pi n k3 pi n k2 pi n k1 pi n k0 page 118 (0x105) portj portj7 portj6 portj5 portj4 portj3 portj2 portj1 portj0 page 118 (0x104) ddrj ddj7 ddj6 ddj5 ddj4 ddj3 ddj2 ddj1 ddj0 page 118 (0x103) pi n jpi n j7 pi n j6 pi n j5 pi n j4 pi n j3 pi n j2 pi n j1 pi n j0 page 118 (0x102) porth porth7 porth6 porth5 porth4 porth3 porth2 porth1 porth0 page 117
11 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 (0x101) ddrh ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 page 117 (0x100) pi n hpi n h7 pi n h6 pi n h5 pi n h4 pi n h3 pi n h2 pi n h1 pi n h0 page 117 (0xff) reserved - - - - - - - - (0xfe) reserved - - - - - - - - (0xfd) reserved - - - - - - - - (0xfc) reserved - - - - - - - - (0xfb) reserved - - - - - - - - (0xfa) reserved - - - - - - - - (0xf9) reserved - - - - - - - - (0xf8) reserved - - - - - - - - (0xf7) reserved - - - - - - - - (0xf6) reserved - - - - - - - - (0xf5) reserved - - - - - - - - (0xf4) reserved - - - - - - - - (0xf3) reserved - - - - - - - - (0xf2) reserved - - - - - - - - (0xf1) reserved - - - - - - - - (0xf0) reserved - - - - - - - - (0xef) reserved - - - - - - - - (0xee) reserved - - - - - - - - (0xed) reserved - - - - - - - - (0xec) reserved - - - - - - - - (0xeb) reserved - - - - - - - (0xea) reserved - - - - - - - - (0xe9) reserved - - - - - - - - (0xe8) reserved - - - - - - - - (0xe7) reserved - - - - - - - (0xe6) reserved - - - - - - - - (0xe5) reserved - - - - - - - - (0xe4) reserved - - - - - - - - (0xe3) reserved - - - - - - - (0xe2) reserved - - - - - - - - (0xe1) reserved - - - - - - - (0xe0) reserved - - - - - - - (0xdf) reserved - - - - - - - - (0xde) reserved - - - - - - - - (0xdd) reserved - - - - - - - (0xdc) reserved - - - - - - - - (0xdb) reserved - - - - - - - - (0xda) reserved - - - - - - - - (0xd9) reserved - - - - - - - (0xd8) reserved - - - - - - - - (0xd7) reserved - - - - - - - - (0xd6) udr2 usart2 i/o data register page 227 (0xd5) ubrr2h - - - - usart2 baud rate register high byte page 231 (0xd4) ubrr2l usart2 baud rate register low byte page 231 (0xd3) reserved - - - - - - - - (0xd2) ucsr2c umsel21 umsel20 upm21 upm 20 usbs2 ucsz21 ucsz20 ucpol2 page 244 (0xd1) ucsr2b rxcie2 txcie2 udrie2 rxe n 2txe n 2 ucsz22 rxb82 txb82 page 243 (0xd0) ucsr2a rxc2 txc2 udre2 fe2 dor2 upe2 u2x2 mpcm2 page 242 (0xcf) reserved - - - - - - - - (0xce) udr1 usart1 i/o data register page 227 (0xcd) ubrr1h - - - - usart1 baud rate register high byte page 231 (0xcc) ubrr1l usart1 baud rate register low byte page 231 (0xcb) reserved - - - - - - - - (0xca) ucsr1c umsel11 umsel10 upm11 upm 10 usbs1 ucsz11 ucsz10 ucpol1 page 244 (0xc9) ucsr1b rxcie1 txcie1 udrie1 rxe n 1txe n 1 ucsz12 rxb81 txb81 page 243 (0xc8) ucsr1a rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 page 242 (0xc7) reserved - - - - - - - - (0xc6) udr0 usart0 i/o data register page 227 (0xc5) ubrr0h - - - - usart0 baud rate register high byte page 231 (0xc4) ubrr0l usart0 baud rate register low byte page 231 (0xc3) reserved - - - - - - - - (0xc2) ucsr0c umsel01 umsel00 upm01 upm 00 usbs0 ucsz01 ucsz00 ucpol0 page 244 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxe n 0txe n 0 ucsz02 rxb80 txb80 page 243 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 page 243 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
12 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 (0xbf) reserved - - - - - - - - (0xbe) reserved - - - - - - - - (0xbd) t w amr t w am6 t w am5 t w am4 t w am3 t w am2 t w am1 t w am0 - page 274 (0xbc) t w cr t w i n tt w ea t w sta t w sto t ww ct w e n -t w ie page 271 (0xbb) t w dr 2-wire serial interface data register page 273 (0xba) t w ar t w a6 t w a5 t w a4 t w a3 t w a2 t w a1 t w a0 t w gce page 273 (0xb9) t w sr t w s7 t w s6 t w s5 t w s4 t w s3 -t w ps1 t w ps0 page 272 (0xb8) t w br 2-wire serial interface bit rate register page 271 (0xb7) reserved - - - - - - - - (0xb6) assr -exclkas2tc n 2ub ocr2aub ocr2bub tcr2aub tcr2bub page 188 (0xb5) reserved - - - - - - - - (0xb4) ocr2b timer/counter2 output compare register b page 195 (0xb3) ocr2a timer/counter2 output compare register a page 195 (0xb2) tc n t2 timer/counter2 (8 bit) page 195 (0xb1) tccr2b foc2a foc2b - - w gm22 cs22 cs21 cs20 page 194 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 - - w gm21 w gm20 page 195 (0xaf) reserved - - - - - - - - (0xae) reserved - - - - - - - - (0xad) ocr4ch timer/counter4 - output compare register c high byte page 167 (0xac) ocr4cl timer/counter4 - output compare register c low byte page 167 (0xab) ocr4bh timer/counter4 - output compare register b high byte page 166 (0xaa) ocr4bl timer/counter4 - output compare register b low byte page 166 (0xa9) ocr4ah timer/counter4 - output compare register a high byte page 166 (0xa8) ocr4al timer/counter4 - output compare register a low byte page 166 (0xa7) icr4h timer/counter4 - input capture register high byte page 168 (0xa6) icr4l timer/counter4 - input capture register low byte page 168 (0xa5) tc n t4h timer/counter4 - counter register high byte page 165 (0xa4) tc n t4l timer/counter4 - counter register low byte page 165 (0xa3) reserved - - - - - - - - (0xa2) tccr4c foc4a foc4b foc4c - - - - - page 164 (0xa1) tccr4b ic n c4 ices4 - w gm43 w gm42 cs42 cs41 cs40 page 162 (0xa0) tccr4a com4a1 com4a0 com4b1 com4b0 com4c1 com4c0 w gm41 w gm40 page 160 (0x9f) reserved - - - - - - - - (0x9e) reserved - - - - - - - - (0x9d) ocr3ch timer/counter3 - output compare register c high byte page 166 (0x9c) ocr3cl timer/counter3 - output compare register c low byte page 166 (0x9b) ocr3bh timer/counter3 - output compare register b high byte page 166 (0x9a) ocr3bl timer/counter3 - output compare register b low byte page 166 (0x99) ocr3ah timer/counter3 - output compare register a high byte page 166 (0x98) ocr3al timer/counter3 - output compare register a low byte page 166 (0x97) icr3h timer/counter3 - input capture register high byte page 168 (0x96) icr3l timer/counter3 - input capture register low byte page 168 (0x95) tc n t3h timer/counter3 - counter register high byte page 165 (0x94) tc n t3l timer/counter3 - counter register low byte page 165 (0x93) reserved - - - - - - - - (0x92) tccr3c foc3a foc3b foc3c - - - - - page 164 (0x91) tccr3b ic n c3 ices3 - w gm33 w gm32 cs32 cs31 cs30 page 162 (0x90) tccr3a com3a1 com3a0 com3b1 com3b0 com3c1 com3c0 w gm31 w gm30 page 160 (0x8f) reserved - - - - - - - - (0x8e) reserved - - - - - - - - (0x8d) ocr1ch timer/counter1 - output compare register c high byte page 166 (0x8c) ocr1cl timer/counter1 - output compare register c low byte page 166 (0x8b) ocr1bh timer/counter1 - output compare register b high byte page 166 (0x8a) ocr1bl timer/counter1 - output compare register b low byte page 166 (0x89) ocr1ah timer/counter1 - output compare register a high byte page 166 (0x88) ocr1al timer/counter1 - output compare register a low byte page 166 (0x87) icr1h timer/counter1 - input capture register high byte page 168 (0x86) icr1l timer/counter1 - input capture register low byte page 168 (0x85) tc n t1h timer/counter1 - counter register high byte page 165 (0x84) tc n t1l timer/counter1 - counter register low byte page 165 (0x83) reserved - - - - - - - - (0x82) tccr1c foc1a foc1b foc1c - - - - - page 164 (0x81) tccr1b ic n c1 ices1 - w gm13 w gm12 cs12 cs11 cs10 page 162 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 com1c1 com1c0 w gm11 w gm10 page 160 (0x7f) didr1 - - - - - -ai n 1d ai n 0d page 278 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d page 300 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
13 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 (0x7d) didr2 adc15d adc14d adc13d adc12d adc11d adc10d adc9d adc8d page 300 (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 page 294 (0x7b) adcsrb -acme - - mux5 adts2 adts1 adts0 page 277,295,,299 (0x7a) adcsra ade n adsc adate adif adie adps2 adps1 adps0 page 297 (0x79) adch adc data register high byte page 298 (0x78) adcl adc data register low byte page 298 (0x77) reserved - - - - - - - - (0x76) reserved - - - - - - - - (0x75) xmcrb xmbk - - - - xmm2 xmm1 xmm0 page 36 (0x74) xmcra sre srl2 srl1 srl0 sr w 11 sr w 10 sr w 01 sr w 00 page 34 (0x73) timsk5 - -icie5 - ocie5c ocie5b ocie5a toie5 page 169 (0x72) timsk4 - -icie4 - ocie4c ocie4b ocie4a toie4 page 169 (0x71) timsk3 - -icie3 - ocie3c ocie3b ocie3a toie3 page 169 (0x70) timsk2 - - - - - ocie2b ocie2a toie2 page 197 (0x6f) timsk1 - -icie1 - ocie1c ocie1b ocie1a toie1 page 169 (0x6e) timsk0 - - - - - ocie0b ocie0a toie0 page 135 (0x6d) pcmsk2 pci n t23 pci n t22 pci n t21 pci n t20 pci n t19 pci n t18 pci n t17 pci n t16 page 81 (0x6c) pcmsk1 pci n t15 pci n t14 pci n t13 pci n t12 pci n t11 pci n t10 pci n t9 pci n t8 page 81 (0x6b) pcmsk0 pci n t7 pci n t6 pci n t5 pci n t4 pci n t3 pci n t2 pci n t1 pci n t0 page 82 (0x6a) eicrb isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 page 79 (0x69) eicra isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 page 78 (0x68) pcicr - - - - - pcie2 pcie1 pcie0 page 80 (0x67) reserved - - - - - - - - (0x66) osccal oscillator calibration register page 48 (0x65) prr1 - - prtim5 prtim4 prtim3 prusart3 prusart2 prusart1 page 56 (0x64) prr0 prt w i prtim2 prtim0 - prtim1 prspi prusart0 pradc page 55 (0x63) reserved - - - - - - - - (0x62) reserved - - - - - - - - (0x61) clkpr clkpce - - - clkps3 clkps2 clkps1 clkps0 page 48 (0x60) w dtcsr w dif w die w dp3 w dce w de w dp2 w dp1 w dp0 page 66 0x3f (0x5f) sreg i t h s v n z c page 12 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 page 14 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 14 0x3c (0x5c) ei n d - - - - - - -ei n d0 page 15 0x3b (0x5b) rampz - - - - - - rampz1 rampz0 page 15 0x3a (0x5a) reserved - - - - - - - - 0x39 (0x59) reserved - - - - - - - - 0x38 (0x58) reserved - - - - - - - - 0x37 (0x57) spmcsr spmie r ww sb sigrd r ww sre blbset pg w rt pgers spme n page 340 0x36 (0x56) reserved - - - - - - - - 0x35 (0x55) mcucr jtd - -pud - - ivsel ivce page 66,76,115,314 0x34 (0x54) mcusr - - -jtrf w drf borf extrf porf page 314 0x33 (0x53) smcr - - - - sm2 sm1 sm0 se page 51 0x32 (0x52) reserved - - - - - - - - 0x31 (0x51) ocdr ocdr7 ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr0 page 307 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 page 277 0x2f (0x4f) reserved - - - - - - - - 0x2e (0x4e) spdr spi data register page 208 0x2d (0x4d) spsr spif w col - - - - - spi2x page 207 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 page 206 0x2b (0x4b) gpior2 general purpose i/o register 2 page 34 0x2a (0x4a) gpior1 general purpose i/o register 1 page 34 0x29 (0x49) reserved - - - - - - - - 0x28 (0x48) ocr0b timer/counter0 output compare register b page 134 0x27 (0x47) ocr0a timer/counter0 output compare register a page 134 0x26 (0x46) tc n t0 timer/counter0 (8 bit) page 134 0x25 (0x45) tccr0b foc0a foc0b - - w gm02 cs02 cs01 cs00 page 133 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 - - w gm01 w gm00 page 130 0x23 (0x43) gtccr tsm - - - - - psrasy psrsy n c page 173, 198 0x22 (0x42) eearh - - - - eeprom address register high byte page 32 0x21 (0x41) eearl eeprom address register low byte page 32 0x20 (0x40) eedr eeprom data register page 32 0x1f (0x3f) eecr - - eepm1 eepm0 eerie eempe eepe eere page 32 0x1e (0x3e) gpior0 general purpose i/o register 0 page 34 0x1d (0x3d) eimsk i n t7 i n t6 i n t5 i n t4 i n t3 i n t2 i n t1 i n t0 page 79 0x1c (0x3c) eifr i n tf7 i n tf6 i n tf5 i n tf4 i n tf3 i n tf2 i n tf1 i n tf0 page 80 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
14 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 n ote: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using th e sbi and cbi instructions. in these reg - isters, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. n ote that the cbi and sbi in structions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 4. w hen using the i/o specific commands i n and out, the i/o addresses $00 - $3f must be used. w hen addressing i/o regis- ters as data space using ld and st instructio ns, $20 must be added to these addresses. the atmega640/1280/1281/2560/2561 is a complex microcontroller with more peri pheral units than can be supported within the 64 location reserved in opcode for the i n and out instructions. for the extended i/o space from $60 - $1ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1b (0x3b) pcifr - - - - - pcif2 pcif1 pcif0 page 81 0x1a (0x3a) tifr5 - -icf5 - ocf5c ocf5b ocf5a tov5 page 169 0x19 (0x39) tifr4 - -icf4 - ocf4c ocf4b ocf4a tov4 page 170 0x18 (0x38) tifr3 - -icf3 - ocf3c ocf3b ocf3a tov3 page 170 0x17 (0x37) tifr2 - - - - - ocf2b ocf2a tov2 page 197 0x16 (0x36) tifr1 - -icf1 - ocf1c ocf1b ocf1a tov1 page 170 0x15 (0x35) tifr0 - - - - - ocf0b ocf0a tov0 page 135 0x14 (0x34) portg - - portg5 portg4 portg3 portg2 portg1 portg0 page 117 0x13 (0x33) ddrg - - ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 page 117 0x12 (0x32) pi n g - -pi n g5 pi n g4 pi n g3 pi n g2 pi n g1 pi n g0 page 117 0x11 (0x31) portf portf7 portf6 portf5 por tf4 portf3 portf2 portf1 portf0 page 116 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 page 117 0x0f (0x2f) pi n fpi n f7 pi n f6 pi n f5 pi n f4 pi n f3 pi n f2 pi n f1 pi n f0 page 117 0x0e (0x2e) porte porte7 porte6 porte5 por te4 porte3 porte2 porte1 porte0 page 116 0x0d (0x2d) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 page 116 0x0c (0x2c) pi n epi n e7 pi n e6 pi n e5 pi n e4 pi n e3 pi n e2 pi n e1 pi n e0 page 116 0x0b (0x2b) portd portd7 portd6 portd5 por td4 portd3 portd2 portd1 portd0 page 116 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 page 116 0x09 (0x29) pi n dpi n d7 pi n d6 pi n d5 pi n d4 pi n d3 pi n d2 pi n d1 pi n d0 page 116 0x08 (0x28) portc portc7 portc6 portc5 por tc4 portc3 portc2 portc1 portc0 page 116 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 page 116 0x06 (0x26) pi n cpi n c7 pi n c6 pi n c5 pi n c4 pi n c3 pi n c2 pi n c1 pi n c0 page 116 0x05 (0x25) portb portb7 portb6 portb5 por tb4 portb3 portb2 portb1 portb0 page 115 0x04 (0x24) ddrb ddb7 ddb6 ddb5 d db4 ddb3 ddb2 ddb1 ddb0 page 115 0x03 (0x23) pi n bpi n b7 pi n b6 pi n b5 pi n b4 pi n b3 pi n b2 pi n b1 pi n b0 page 115 0x02 (0x22) porta porta7 porta6 porta5 por ta4 porta3 porta2 porta1 porta0 page 115 0x01 (0x21) ddra dda7 dda6 dda5 d da4 dda3 dda2 dda1 dda0 page 115 0x00 (0x20) pi n api n a7 pi n a6 pi n a5 pi n a4 pi n a3 pi n a2 pi n a1 pi n a0 page 115 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
15 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c, n ,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c, n ,v,h 1 adi w rdl,k add immediate to w ord rdh:rdl rdh:rdl + k z,c, n ,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c, n ,v,h 1 subi rd, k subtract constant from register rd rd - k z,c, n ,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c, n ,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c, n ,v,h 1 sbi w rdl,k subtract immediate from w ord rdh:rdl rdh:rdl - k z,c, n ,v,s 2 a n d rd, rr logical a n d registers rd rd ? rr z, n ,v 1 a n di rd, k logical a n d register and constant rd rd ? kz, n ,v 1 or rd, rr logical or registers rd rd v rr z, n ,v 1 ori rd, k logical or register and constant rd rd v k z, n ,v 1 eor rd, rr exclusive or registers rd rd rr z, n ,v 1 com rd one?s complement rd 0xff ? rd z,c, n ,v 1 n eg rd two?s complement rd 0x00 ? rd z,c, n ,v,h 1 sbr rd,k set bit(s) in register rd rd v k z, n ,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z, n ,v 1 i n c rd increment rd rd + 1 z, n ,v 1 dec rd decrement rd rd ? 1 z, n ,v 1 tst rd test for zero or minus rd rd ? rd z, n ,v 1 clr rd clear register rd rd rd z, n ,v 1 ser rd set register rd 0xff n one 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 n one 2 ijmp indirect jump to (z) pc z n one 2 eijmp extended indirect jump to (z) pc (ei n d:z) n one 2 jmp k direct jump pc k n one 3 rcall k relative subroutine call pc pc + k + 1 n one 4 icall indirect call to (z) pc z n one 4 eicall extended indirect call to (z) pc (ei n d:z) n one 4 call k direct subroutine call pc k n one 5 ret subroutine return pc stack n one 5 reti interrupt return pc stack i 5 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 n one 1/2/3 cp rd,rr compare rd ? rr z, n ,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n ,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n ,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 n one 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 n one 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 n one 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 n one 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 n one 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 n one 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 n one 1/2 br n e k branch if n ot equal if (z = 0) then pc pc + k + 1 n one 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 n one 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 n one 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 n one 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 n one 1/2 brmi k branch if minus if ( n = 1) then pc pc + k + 1 n one 1/2 brpl k branch if plus if ( n = 0) then pc pc + k + 1 n one 1/2 brge k branch if greater or equal, signed if ( n v= 0) then pc pc + k + 1 n one 1/2 brlt k branch if less than zero, signed if ( n v= 1) then pc pc + k + 1 n one 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 n one 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 n one 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 n one 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 n one 1/2
16 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 n one 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 n one 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 n one 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 n one 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1 n one 2 cbi p,b clear bit in i/o register i/o(p,b) 0 n one 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c, n ,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c, n ,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c, n ,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c, n ,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c, n ,v 1 s w ap rd swap n ibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) n one 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t n one 1 sec set carry c 1c1 clc clear carry c 0 c 1 se n set n egative flag n 1 n 1 cl n clear n egative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr n one 1 mov w rd, rr copy register w ord rd+1:rd rr+1:rr n one 1 ldi rd, k load immediate rd k n one 1 ld rd, x load indirect rd (x) n one 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 n one 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) n one 2 ld rd, y load indirect rd (y) n one 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 n one 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) n one 2 ldd rd,y+q load indirect with displacement rd (y + q) n one 2 ld rd, z load indirect rd (z) n one 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 n one 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) n one 2 ldd rd, z+q load indirect with displacement rd (z + q) n one 2 lds rd, k load direct from sram rd (k) n one 2 st x, rr store indirect (x) rr n one 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 n one 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr n one 2 st y, rr store indirect (y) rr n one 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 n one 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr n one 2 std y+q,rr store indirect with displacement (y + q) rr n one 2 st z, rr store indirect (z) rr n one 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 n one 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr n one 2 std z+q,rr store indirect with displacement (z + q) rr n one 2 sts k, rr store direct to sram (k) rr n one 2 lpm load program memory r0 (z) n one 3 lpm rd, z load program memory rd (z) n one 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 n one 3 elpm extended load program memory r0 (rampz:z) n one 3 elpm rd, z extended load program memory rd (rampz:z) n one 3 mnemonics operands description operation flags #clocks
17 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 n ote: eicall and eijmp do not exist in atmega640/1280/1281. elpm does not exist in atmega640. elpm rd, z+ extended load program memory rd (rampz:z), rampz:z rampz:z+1 n one 3 spm store program memory (z) r1:r0 n one - i n rd, p in port rd p n one 1 out p, rr out port p rr n one 1 push rr push register on stack stack rr n one 2 pop rd pop register from stack rd stack n one 2 mcu control instructions n op n o operation n one 1 sleep sleep (see specific descr. for sleep function) n one 1 w dr w atchdog reset (see specific descr. for w dr/timer) n one 1 break break for on-chip debug only n one n /a mnemonics operands description operation flags #clocks
18 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 ordering information n otes: 1. this device can also be supplied in wafer form. please c ontact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. see ?maximum speed vs. vcc? on page 377. 3. pb-free packaging, complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. atmega640 speed (mhz) (2) power supply ordering code package (1)(3) operation range 8 1.8 - 5.5v atmega640v-8au atmega640v-8cu 100a 100c1 industrial ( -40 c to 85 c) 16 2.7 - 5.5v atmega640-16au atmega640-16cu 100a 100c1 industrial ( -40 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 64m2 64-pad, 9 x 9 x 1.0 mm body, quad flat n o-lead/micro lead frame package (qf n /mlf) 100a 100-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 100c1 100-ball, chip ball grid array (cbga)
19 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 n otes: 1. this device can also be supplied in wafer form. please c ontact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. see ?maximum speed vs. vcc? on page 377. 3. pb-free packaging, complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. atmega1281 speed (mhz) (2) power supply ordering code package (1)(3) operation range 8 1.8 - 5.5v atmega1281v-8au atmega1281v-8mu 64a 64m2 industrial ( -40 c to 85 c) 16 2.7 - 5.5v atmega1281-16au atmega1281-16mu 64a 64m2 industrial ( -40 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 64m2 64-pad, 9 x 9 x 1.0 mm body, quad flat n o-lead/micro lead frame package (qf n /mlf) 100a 100-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 100c1 100-ball, chip ball grid array (cbga)
20 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 n otes: 1. this device can also be supplied in wafer form. please c ontact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. see ?maximum speed vs. vcc? on page 377. 3. pb-free packaging, complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. atmega1280 speed (mhz) (2) power supply ordering code package (1)(3) operation range 8 1.8 - 5.5v atmega1280v-8au atmega1280v-8cu 100a 100c1 industrial ( -40 c to 85 c) 16 2.7 - 5.5v atmega1280-16au atmega1280-16au 100a 100c1 industrial ( -40 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 64m2 64-pad, 9 x 9 x 1.0 mm body, quad flat n o-lead/micro lead frame package (qf n /mlf) 100a 100-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 100c1 100-ball, chip ball grid array (cbga)
21 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 n otes: 1. this device can also be supplied in wafer form. please c ontact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. see ?maximum speed vs. vcc? on page 377. 3. pb-free packaging, complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. atmega2561 speed (mhz) (2) power supply ordering code package (1)(3) operation range 8 1.8 - 5.5v ATMEGA2561V-8AU atmega2561v-8mu 64a 64m2 industrial ( -40 c to 85 c) 16 4.5 - 5.5v atmega2561-16au atmega2561-16mu 64a 64m2 industrial ( -40 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 64m2 64-pad, 9 x 9 x 1.0 mm body, quad flat n o-lead/micro lead frame package (qf n /mlf) 100a 100-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 100c1 100-ball, chip ball grid array (cbga)
22 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 n otes: 1. this device can also be supplied in wafer form. please c ontact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. see ?maximum speed vs. vcc? on page 377. 3. pb-free packaging, complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. atmega2560 speed (mhz) (2) power supply ordering code package (1)(3) operation range 8 1.8 - 5.5v atmega2560v-8au atmega2560v-8cu 100a 100c1 industrial ( -40 c to 85 c) 16 4.5 - 5.5v atmega2560-16au atmega2560-16cu 100a 100c1 industrial ( -40 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 64m2 64-pad, 9 x 9 x 1.0 mm body, quad flat n o-lead/micro lead frame package (qf n /mlf) 100a 100-lead, thin (1.0 mm) plastic gull w ing quad flat package (tqfp) 100c1 100-ball, chip ball grid array (cbga)
23 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 packaging information 100a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 100a, 100-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.5 mm lead pitch, thin profile plastic quad flat package (tqfp) c 100a 10/5/2001 pi n 1 ide n tifier 0?~7? pi n 1 l c a1 a2 a d1 d e e1 e b a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 n ote 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 n ote 2 b 0.17 ? 0.27 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.50 typ n otes: 1. this package conforms to jedec reference ms-026, variation aed. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.08 mm maximum. common dimensions (unit of measure = mm) symbol min nom max note
24 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 100c1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 100c1 , 100-ball, 9 x 9 x 1.2 mm body, ball pitch 0.80 mm chip array bga package (cbga) a 100c1 5/25/06 top view side view bottom view common dimensions (unit of measure = mm) symbol min nom max note a 1.10 ? 1.20 a1 0.30 0.35 0.40 d 8.90 9.00 9.10 e 8.90 9.00 9.10 d1 7.10 7.20 7.30 e1 7.10 7.20 7.30 ? b 0.35 0.40 0.45 e 0.80 typ marked a1 identifier 1 2 3 4 5 6 7 8 a b c d e 9 f g h i j 10 0.90 typ 0.90 typ a1 corner 0.12 z e d e e ?b a a1 e1 d1
25 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 64a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64a, 64-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 64a 10/5/2001 pi n 1 ide n tifier 0?~7? pi n 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note n otes: 1. this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 n ote 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 n ote 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
26 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 64m2 2325 orchard park w ay san jose, ca 95131 title drawing no. r rev. 64m2 , 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, d 64m2 5/25/06 common dimen s ion s (unit of meas u re = mm) s ymbol min nom max note a 0. 8 0 0.90 1.00 a1 ? 0.02 0.05 b 0.1 8 0.25 0.30 d d2 7.50 7.65 7. 8 0 8 .90 9.00 9.10 8 .90 9.00 9.10 e e2 7.50 7.65 7. 8 0 e 0.50 bsc l 0.35 0.40 0.45 top view s ide view bottom view d e marked pin# 1 id seating plane a1 c a c 0.0 8 1 2 3 k 0.20 0.27 0.40 2. dimension and tolerance conform to asmey14.5m-1994. e2 d2 b e pin #1 corner l pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k note: 1. jedec standard mo-220, (saw sing u lation) fig. 1, v mmd. 7.65 mm exposed pad, micro lead frame package (mlf)
27 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 errata atmega640 rev. a ? inaccurate adc conversion in diff erential mode with 200x gain ? high current consum ption in sleep mode 1. inaccurate adc conversion in differential mode with 200x gain w ith avcc < 3.6v, random conversions will be inaccurate. typical absolute accu- racy may reach 64 lsb. problem fix/workaround n one 2. high current consumption in sleep mode. if a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the sleep instruc- tion directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. atmega1280 rev. a ? inaccurate adc conversion in diff erential mode with 200x gain ? high current consum ption in sleep mode 1. inaccurate adc conversion in differential mode with 200x gain w ith avcc < 3.6v, random conversions will be inaccurate. typical absolute accu- racy may reach 64 lsb. problem fix/workaround n one 2. high current consumption in sleep mode. if a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the sleep instruc- tion directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled.
28 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 atmega1281 rev. a ? inaccurate adc conversion in diff erential mode with 200x gain ? high current consum ption in sleep mode 1. inaccurate adc conversion in differential mode with 200x gain w ith avcc < 3.6v, random conversions will be inaccurate. typical absolute accu- racy may reach 64 lsb. problem fix/workaround n one 2. high current consumption in sleep mode. if a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the sleep instruc- tion directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. atmega2560 rev. e n o known errata. atmega2560 rev. d n ot sampled. atmega2560 rev. c ? high current consum ption in sleep mode 1. high current consumption in sleep mode. if a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the sleep instruc- tion directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. atmega2560 rev. b n ot sampled.
29 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 atmega2560 rev. a ? non-read-while-write area of flash not functional ? part does not work under 2.4 volts ? incorrect adc reading in differential mode ? internal adc reference has too low value ? in/out instructions may be executed twice when stack is in external ram ? eeprom read from application code does not work in lock bit mode 3 1. non-read-while-write area of flash not functional the n on-read- w hile- w rite area of the flash is not working as expected. the prob- lem is related to the speed of the part when reading the flash of this area. problem fix/workaround - only use the first 248k of the flash. - if boot functionality is needed, run the code in the n on-read- w hile- w rite area at maximum 1/4th of the maximum frequency of the device at any given voltage. this is done by writing the clkpr register before entering the boot section of the code 2. part does not work under 2.4 volts the part does not execute code correctly below 2.4 volts problem fix/workaround do not use the part at voltages below 2.4 volts. 3. incorrect adc reading in differential mode the adc has high noise in differential mode. it can give up to 7 lsb error. problem fix/workaround use only the 7 msb of the result when using the adc in differential mode. 4. internal adc reference has too low value the internal adc reference has a value lower than specified problem fix/workaround - use avcc or external reference - the actual value of the reference can be measured by applying a known voltage to the adc when using the internal reference. the result when doing later conversions can then be calibrated. 5. in/out instructions may be executed twice when stack is in external ram if either an i n or an out instruction is executed directly before an interrupt occurs and the stack pointer is located in external ram, the instruction will be executed twice. in some cases this will cause a problem, for example: - if reading sreg it will appear that the i-flag is cleared. - if writing to the pi n registers, the po rt will toggle twice. - if reading registers with interrupt flags, the flags will appea r to be cleared. problem fix/workaround there are two application work-arounds, where selecting one of them, will be omit- ting the issue: - replace i n and out with ld/lds/ldd and st/sts/std instructions - use internal ram for stack pointer.
30 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 6. eeprom read from applic ation code does not work in lock bit mode 3 w hen the memory lock bits lb2 and lb1 are programmed to mode 3, eeprom read does not work from the application code. problem fix/workaround do not set lock bit protection mode 3 when the application code needs to read from eeprom. atmega2561 rev. e n o known errata. atmega2561 rev. d n ot sampled. atmega2561 rev. c ? high current consum ption in sleep mode 1. high current consumption in sleep mode. if a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the sleep instruc- tion directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. atmega2561 rev. b n ot sampled. atmega2561 rev. a ? non-read-while-write area of flash not functional ? part does not work under 2.4 volts ? incorrect adc reading in differential mode ? internal adc reference has too low value ? in/out instructions may be executed twice when stack is in external ram ? eeprom read from application code does not work in lock bit mode 3 1. non-read-while-write area of flash not functional the n on-read- w hile- w rite area of the flash is not working as expected. the prob- lem is related to the speed of the part when reading the flash of this area. problem fix/workaround - only use the first 248k of the flash. - if boot functionality is needed, run the code in the n on-read- w hile- w rite area at maximum 1/4th of the maximum frequency of the device at any given voltage. this is done by writing the clkpr register before entering the boot section of the code.
31 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 2. part does not work under 2.4 volts the part does not execute code correctly below 2.4 volts problem fix/workaround do not use the part at voltages below 2.4 volts. 3. incorrect adc reading in differential mode the adc has high noise in differential mode. it can give up to 7 lsb error. problem fix/workaround use only the 7 msb of the result when using the adc in differential mode 4. internal adc reference has too low value the internal adc reference has a value lower than specified problem fix/workaround - use avcc or external reference - the actual value of the reference can be measured by applying a known voltage to the adc when using the internal reference. the result when doing later conversions can then be calibrated. 5. in/out instructions may be executed twice when stack is in external ram if either an i n or an out instruction is executed directly before an interrupt occurs and the stack pointer is located in external ram, the instruction will be executed twice. in some cases this will cause a problem, for example: - if reading sreg it will appear that the i-flag is cleared. - if writing to the pi n registers, the po rt will toggle twice. - if reading registers with interrupt flags, the flags will appea r to be cleared. problem fix/workaround there are two app lication workarounds, where sele cting one of them, will be omit- ting the issue: - replace i n and out with ld/lds/ldd and st/sts/std instructions - use internal ram for stack pointer. 6. eeprom read from applic ation code does not work in lock bit mode 3 w hen the memory lock bits lb2 and lb1 are programmed to mode 3, eeprom read does not work from the application code. problem fix/workaround do not set lock bit protection mode 3 when the application code needs to read from eeprom.
32 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 datasheet revision history please note that the referring page numbers in this section are referring to this docu- ment.the referring revision in this section are referring to the document revision. rev. 2549k-01/07 rev. 2549j-09/06 rev. 2549i-07/06 rev. 2549h-06/06 rev. 2549g-06/06 1. updated table 1 on page 3. 2. updated ?pin descriptions? on page 7. 3. updated ?stack pointer? on page 14. 4. updated ?bit 1 ? eepe: eeprom programming enable ? on page 33. 5. updated assembly code example in ?watchdog timer? on page 62. 6: updated ?eimsk ? external interrupt mask register? on page 79. 7. updated bit description in ?pcifr ? pin change interrupt flag register? on page 81. 8. updated code example in ?usart initialization? on page 215. 9. updated figure 120 on page 288. 10. updated ?dc characteristics? on page 374. 1. updated ?calibrated internal rc oscillator? on page 44. 2. updated code example in ?moving interrupts between application and boot section? on page 74. 3. updated ?timer/counter prescaler? on page 190. 4. updated ?device identification register? on page 309. 5. updated ?signature bytes? on page 345. 6. updated ?instruction set summary? on page 421. 1. updated table 74 on page 130, table 77 on page 131, table 79 on page 132, table 82 on page 149, table 84 on page 161, table 85 on page 161, table 89 on page 191, table 92 on page 192 and table 94 on page 193. 2. updated ?fast pwm mode? on page 151. 1. updated ?calibrated internal rc oscillator? on page 44. 2. updated ?osccal ? oscillator ca libration register? on page 48. 3. added table 172 on page 384. 1. updated ?features? on page 1. 2. added figure 2 on page 3, table 1 on page 3. 3. updated ?calibrated internal rc oscillator? on page 44. 4. updated ?power management and sleep modes? on page 50. 5. updated note for table 30 on page 67. 6. updated figure 121 on page 289 and figure 122 on page 289. 7. updated ?setting the boot loader lock bits by spm? on page 330.
33 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 rev. 2549f-04/06 rev. 2549e-04/06 rev. 2549d-12/05 rev. 2549c-09/05 8. updated ?ordering information? on page 18. 9. added package information ?100c1? on page 24. 10. updated ?errata? on page 27. 1. updated figure 15 on page 28, figure 16 on page 29 and figure 17 on page 29. 2. updated table 88 on page 191 and table 89 on page 191. 3. updated features in ?adc ? analog to digital converter? on page 279. 4. updated ?fuse bits? on page 343. 1. updated ?features? on page 1. 2. updated table 27 on page 60. 3. updated note for table 27 on page 60. 4. updated ?bit 6 ? acbg: analog comparator bandgap select? on page 277. 5. updated ?prescaling and conversion timing? on page 282. 5. updated ?maximum speed vs. vcc? on page 377. 6. updated ?ordering information? on page 18. 1. advanced information status changed to preliminary. 2. changed number of i/o ports from 51 to 54. 3. updatet typos in ?tccr0a ? timer/co unter control register a? on page 130. 4. updated features in ?adc ? analog to digital converter? on page 279. 5. updated operation in?adc ? analog to digital converter? on page 279 6. updated stabilizing time in ?chang ing channel or reference selection? on page 286. 7. updated figure 113 on page 280, figure 121 on page 289, figure 122 on page 289. 8. updated text in ?adcsrb ? adc cont rol and status register b? on page 295. 9. updated note for table 4 on page 41, table 51 on page 99, table 128 on page 294 and table 131 on page 299. 10. updated table 170 on page 382 and table 171 on page 383. 11. updated ?filling the temporary buffer (page loading)? on page 329. 12. updated ?typical characteristics? on page 390. 13. updated ?packaging information? on page 23. 14. updated ?errata? on page 27. 1. updated speed grade in section ?features? on page 1. 2. added ?resources? on page 9. 3. updated ?spi ? serial peripheral interface? on page 199. in slave mode, low and high period spi clock must be larger than 2 cpu cycles.
34 atmega640/1280/1281/2560/2561 2549ks?avr?01/07 rev. 2549b-05/05 rev. 2549a-03/05 4. updated ?bit rate generator unit? on page 251. 5. updated ?maximum speed vs. vcc? on page 377. 6. updated ?ordering information? on page 18. 7. updated ?packaging information? on page 23. package 64m1 replaced by 64m2. 8. updated ?errata? on page 27. 1. jtag id/signature for atmega640 updated: 0x9608. 2. updated table 43 on page 94. 3. updated ?serial programming instruction set? on page 359. 4. updated ?errata? on page 27. 1. initial version.
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